1. Field of the Invention
The present invention relates to a semiconductor integrated circuit apparatus, and more particularly, to a semiconductor integrated circuit (referred to as an IC hereinafter) apparatus comprising at least one clock signal line formed in a ring shape for supplying a clock signal to a plurality of flip-flops, which are provided for performing various kinds of signal processing such as digital processing for processing a television signal, a video signal, or the like.
2. Description of the Prior Art
FIG. 1 shows a semiconductor IC chip 10 of a first prior art.
Referring to FIG. 1, the IC chip 10 comprises an external clock input terminal 1, a clock buffer 2, and three groups FG1, FG2 and FG3 of delay-type flip-flops FF1, FF2 and FF3 each flip-flop provided for performing various kinds of signal processing in response to an inputted clock signal. The clock signal inputted through the external clock input terminal 1 is inputted through the clock buffer 2 and clock signal lines 3 to the respective groups FG1, FG2 and FG3 of flip-flops FF1, FF2 and FF3.
In this case, since the clock signal lines 3 are formed in a branching shape or a bus shape, the respective line resistances between the output terminal of the clock buffer 2 and the input terminals of the respective flip-flops FF1, FF2 and FF3 are set to be substantially the same as each other, the respective propagation delay times required when the clock signal propagates from the clock buffer 2 to the respective flip-flops FF1, FF2 and FF3 become substantially the same as each other. This results in reduction in skews of the clock signal (referred to as clock skews hereinafter) in the IC chip 10.
FIG. 2 shows a semiconductor IC chip 11 of a second prior art, wherein the IC chip 11 comprises about 1000 and more delay-type flip-flops FF1, FF2 and FF3. In FIG. 2, the same components as those shown in FIG. 1 are denoted by the same references as those shown in FIG. 1.
Referring to FIG. 2, the clock signal inputted through the external clock input terminal 1 is divided into three clock signals on three clock signal lines 4, and then (a) the first clock signal is inputted through a clock buffer 2a to a first group FG1 of flip-flops FF1, (b) the second clock signal is inputted through a clock buffer 2b to a second group FG2 of flip-flips FF2, and (c) the third clock signal is inputted through a clock buffer 2c to a third group FG3 of flip-flips FF3.
In this case, if only one clock buffer is provided in the IC chip 11, differences among the phase delays at the respective inputs of the flip-flops FF1, FF2 and FF3 becomes too large. Therefore, the respective clock signal lines 4 extending from the external clock input terminal 1 to the respective clock buffers 2a, 2b and 2c are formed in a branching-shape so that the clock signal is divided into a plurality of clock signals through a plurality of clock buffers 2a, 2b and 2c. In this case, since the clock signal lines 4 are formed in the branching shape, the respective line resistances between the external clock input terminal 1 and the respective clock buffers 2a, 2b and 2c are set to be substantially the same as each other. This results in reduction in the clock skews in the IC chip 11.
Further, the numbers of flip-flops FF1, FF2 and FF3 included in respective ones of the groups FG1, FG2 and FG3 are set to be the same as each other, and then, the propagation delays when the clock signal propagates from the respective clock buffers 2a, 2b nand 2c to the respective flip-flops FF1, FF2 and FF3 become substantially the same as each other.
In the above-mentioned IC chip 10, forming the clock signal lines 3 for connecting the clock buffer 2 and the respective flip-flops FF1, FF2 and FF3 in the branching shape leads to reduction in the clock skews. However, when the number of flip-flops is further increased, the differences among the propagation delays of the respective clock signals supplied to the respective flip-flops become larger than a predetermined specification value since the ability of the clock buffer 2 for driving many flip-flops becomes relatively lowered. In this case, in order to eliminate the above problem, the size of the transistor of the output stage of the clock buffer 2 must be made larger. This results in an increase in the ability of the clock buffer 2 for driving the flip-flops, and then the above-mentioned differences among the propagation delays are reduced to the predetermined specification value. However, in this method, there is a limitation. Concretely speaking, there is a limitation when increasing the size of the transistor of the output stage of the clock buffer 2.
Accordingly, in order to eliminate the above-mentioned problem, there should be used a method of forming the clock signal lines 4 in the branching shape, namely, the IC chip 11 of the second prior art shown in FIG. 2 should be used.
However, if the numbers of flip-flops included in respective groups and connected to the respective clock buffers 2a, 2b and 2c are different from each other, there are caused differences among the phase delays at the respective output terminals of the clock buffers 2a, 2b and 2c due to the differences of the loads of the respective clock buffers 2a, 2b and 2c, and then there are generated clock skews at the respective input terminals of the flip-flops FF1-FF3.
As the size of the IC chip becomes larger, the number of the flip-flops included in the IC chip increases. In this case, it is extremely difficult to set the numbers of the flip-flops FF1, FF2 and FF3 respectively connected to the clock buffers 2a, 2b and 2c to be the same as each other.